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- 1 - ts 52002 version 1. 2 s pecifications subject to change www.triunesystems.com copyright ? 201 1 , triune systems, llc description features ? utilizes a temperature - independent pv mppt - lite? regulation scheme ? v ba t reverse current blocking ? up to 1.5a continuous output current ? high efficiency C up to 92% at typical load ? current mode pwm control in constant voltage ? input supply under - voltage lockout ? full protection for vbat over - voltage ? device over - current and over - temperature protection ? i2c status interface ? v bat status indication summary specification ? wide input voltage range: 3.2v to 7.2v ? packaged in a 1 6pin qfn (4x4) typical application the TS52002 is a dc/dc synchronous switching mpp t regulator with fully integrat ed power switches, internal compensation, and fu ll fault protection. the TS52002 utilizes a temperature - independent photovoltaic maximum power point tracking ( mpp t - lite? ) calculator to optimize power output from the source. the switching frequency of 1mhz enables the use of small filter components, result ing in smaller board space and reduced bom costs. applications ? 1 - cell and 2 - cell nimh chargers ? portable solar c hargers ? off - grid systems ? wireless sensor networks ? smoke detectors ? hvac controls high efficiency nimh b attery charger for photovoltaic sources g n d e n s w n f l t v b a t s c l p g n d c o u t l o u t r s e n s e v i n s d a p h o t o v o l t a i c c e l l s v s e n s e r p u l l u p ( o p t i o n a l ) v d d r p u l l u p ( o p t i o n a l ) v d d c i n v d d c v d d t s 5 2 0 0 2 c n i m h C 1 o r 2 c e l l s s e r i e s o r p a r a l l e l
- 2 - ts 52002 version 1. 2 specifications subject to change www.triunesystems.com copyright ? 2011 , triune systems, llc pinout figure 1b: package pinout diagram pin description pin symbol pin # function description sw 1 switching voltage node connected to 4.7uh (typi cal) inductor vin 2 photovoltaic input voltage input voltage v sense 3 current sense positive input positive input for the mpp current loop. v bat 4 output voltage regulator feedback input gnd 5 gnd primary ground for the majority of the device except the low - side power fet. en 6 enable input above 2.2v the device is enabled. gnd the pin to disable the device. includes internal pull - up. nflt 7 inverted fault open - drain output. vdd 8 internal 3.3v supply output connected to 100nf capacitor to gnd 9 unused gnd in application 10 unused gnd in application vin 11 photovoltaic input voltage input voltage scl 12 clock input i2 c clock input. sda 13 data input/output i2 c data open - drain output. sw 14 switching voltage node connected to 4.7uh (typica l) inductor pgnd 15 power gnd gnd supply for internal low - side fet/integrated diode pgnd 16 power gnd gnd supply for internal low - side fet/integrated diode t s 5 2 0 0 2 q f n 1 6 4 x 4 t o p / s y m b o l i z a t i o n v i e w v i n v s e n s e v b a t s w v i n n c n c s c l s w p g n d p g n d s d a n f l t e n g n d v d d
- 3 - ts 52002 version 1. 2 specifications subject to change www.triunesystems.com copyright ? 2011 , triune systems, llc functional block dia gram figure 2 : ts 5 2002 block diagram v i n g a t e d r i v e g a t e d r i v e g a t e d r i v e c o n t r o l v b a t s w o s c i l l a t o r r a m p g e n e r a t o r c o m p a r a t o r e r r o r a m p g n d m o n i t o r & c o n t r o l o v e r v o l t a g e p r o t e c t i o n v b a t v i n v i n ? e n p g n d n f l t c o u t l o u t c o m p e n s a t i o n n e t w o r k b a c k g a t e b l o c k i n g p h o t o v o l t a i c c e l l s ~ 5 v @ 4 5 0 m a v r e f l o a d r s e n s e v s e n s e m p p & c u r r e n t c o n t r o l i 2 c i n t e r f a c e s c l s d a v i n c i n v d d c v d d v d d r e g u l a t o r v i n
- 4 - ts 52002 version 1. 2 specifications subject to change www.triunesystems.com copyright ? 2011 , triune systems, llc absolute maximum rat ings over operating free C air temperature range unless otherwise noted (1,2 ,3 ) parameter range unit vin, en , nflt , scl, sda , v ba t , vsense - 0.3 to 8 v sw - 1 to 8.8 v vdd - 0.3 to 3.6 v operating junction temperature range, t j - 40 to 125 ? c storage temperature range, t stg - 65 to 150 ? c electrostatic discharge C human body model 2k v electrostatic discharge C machine model +/ - 200 v lead temperature (soldering, 10 seconds) 260 ? c (1) stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is n ot implied. exposure to a bsolute C maximum C rated conditions for extended periods may affect device reliability. (2) all voltage values are with respect to network ground terminal. (3) esd testing is performed according to the respective jesd22 jedec standard. thermal character istics symbol parameter value unit ? ja thermal resistance junction to air (note 1) 50 c/w note 1: assumes 4x4 qfn - 16 in 1 in 2 area of 2 oz copper and 25 ? c ambient temperature. recommended operatin g conditions symbol parameter min typ max unit vin ph otovoltaic input operating voltage 3.2 5.3 7.2 v r sense sense resistor 50 m ? l out output filter inductor typical value (note 1) 4.7 uh c out output filter capacitor typical value (note 2) 4.7 uf c out - esr output filter capacitor esr 100 m ? c in i nput supply bypass capacitor typical value (note 3) 3.3 10 uf c vdd vdd supply bypass capacitor value (note 2) 70 100 130 nf t a operating free air temperature - 40 85 ? c t j operating junction temperature - 40 125 ? c note 1: for best performance, an i nductor with a saturation current rating higher than the maximum v ba t load requirement plus the inductor current ripple. note 2: for best performance, a low esr ceramic capacitor should be used. note 3: for best performance, a low esr ceramic capacitor sho uld be used. if c in is not a low esr ceramic capacitor, a 0.1uf ceramic capacitor should be added in parallel to c in .
- 5 - ts 52002 version 1. 2 specifications subject to change www.triunesystems.com copyright ? 2011 , triune systems, llc characteristics electrical characteristics, t j = - 40c to 125c, vin = 5.3v (unless otherwise noted) symbol parameter condition min typ max unit vin supply voltage v in photovoltaic voltage input 3.2 5.3 7.2 v i cc - norm quiescent current normal mode i load = 0a 3 ma i cc - stby quiescent current disable mode en = 0v 15 50 ua v ba t leakage i b at - leak leakage current from output en = 0v 10 ua i b a t - back reverse current v ba t > vin 10 ua vin under - voltage lockout vin - uv input supply under - voltage threshold vin increasing 3.15 v vin - uv_hyst input supply under - voltage threshold hysteresis 100 200 mv osc f osc oscillator frequen cy 0.9 1 1.1 mhz nflt open drain output i oh - nflt high - level output leakage v nflt = 5.3v 0.1 ua v ol - nflt low - level output voltage i nflt = - 1ma 0.4 v en/scl/sda input voltage thresholds v ih high level input voltage 2.2 v v il low level input voltage 0.8 v v hyst input hysteresis 200 mv i in - en input leakage v en =vin 0.1 ua v en =0v - 2.0 ua i in - scl input leakage v scl =vin 55 ua v scl =0v - 0.1 ua i in - sda input leakage v sda =vin 0.1 ua v sda =0v - 0.1 ua v ol - sda low - level outp ut voltage i sda = - 1ma 0.4 v thermal shutdown tsd thermal shutdown junction temperature 150 170 c tsd hyst tsd hysteresis 10 c
- 6 - ts 52002 version 1. 2 specifications subject to change www.triunesystems.com copyright ? 2011 , triune systems, llc charger characterist ics electrical characteristics, t j = - 40c to 125c, vin = 5.3v (unless otherwise noted) sy mbol parameter condition min typ max unit charging regulator: l=4.7uh and c=4.7uf i b a t - fc output current limit i b a t = 1.5 a i b a t - 10 % i b a t i b a t + 10 % a v ba t - to termination voltage 4.16 4.2 4.24 v r dson high side switch on resistance i sw = - 1a, t j =25c 250 m? sw = 1a, t j =25c 150 m? b a t max output current 1.5 a i ocd over - current detect hs switch current 2.5 a v ba t - ov v ba t over - voltage threshold 101% v ba t 102% v ba t 103% v ba t v ba t - ov_hyst v ba t over - voltage hyster esis 0.2 % v ba t 0.4 % v ba t 0.6 % v ba t duty max max duty cycle 99 % i 2 c interface timing r equirements electrical characteristics, t j = - 40c to 125c, vin = 5.3v (unless otherwise noted) symbol parameter standard mode fast mode unit min max min max f scl i 2 c clock frequency 0 100 0 400 khz t sch i 2 c clock high time 4 0.6 s t scl i 2 c clock low time 4.7 1.3 s t sp i 2 c tolerable spike time 0 50 0 50 ns t sds i 2 c serial data setup time 250 100 ns t sdh i 2 c serial data hold time 0 0 s t icr i 2 c i nput rise time 1000 300 ns t icf i 2 c input fall time 300 300 ns t ocf i 2 c output fall time; 10 pf to 400 pf bus 300 300 n s t buf i 2 c bus free time between stop and start 4.7 1.3 s t sts i 2 c start or repeated start condition setup time 4.7 0.6 s t sth i 2 c start or repeated start condition hold time 4 0.6 s t sps i 2 c stop condition setup time 4 0.6 s
- 7 - ts 52002 version 1. 2 specifications subject to change www.triunesystems.com copyright ? 2011 , triune systems, llc functional description the ts 5 2002 is a fully - integrated mpp regulator ic based on a highly - efficient switching topology. it includes a maximum power point t racking (mpp t ) function to optimize its input voltage to extract the maximum possible power from a photovoltaic cell. a 1 mhz internal switching frequency facilitates low - cost lc filter combinations. when the output vol tage is below the termination voltage, the device will regulate to the maximum power point. this will continue as long as the output current is below the current limit and no fault has occurred. in order for the maximum power point (mpp) regulation to be most effective, the output load needs to not allow high frequency transients in output voltage. this will cause the device to operate at a non optimal mpp point until the output voltage has remained stat ic for several milliseconds. as detailed in the ap plication diagram, the external c p ulses the charging current based on a nimh charging profile . the battery voltage and/ or temperature is m onitor ed to safely charge and ensure the battery is fully charged. one or two nimh cells can be con figured in seri es or parallel with a p arallel configuration requiring two switches to allow the c to manage the charging profile . internal protection details internal current limit the current through the inductor is sensed on a cycle by cycle basis and if current l imit is reached, it will abbreviate the cycle. current limit is always active when the regulator is enabled. thermal shutdown if the temperature of the die exceeds 170c (typical), the sw outputs will tri - state to protec t the device from damage. the nf lt and all other protection circuitry will stay active to inform the system of the failure mode. once the device cools to 160c (typical), the device will attempt to start up again. if the device reaches 170c, the shutdown/restart sequence will repeat . vin under - voltage lockout the device is held in the off state until vin reaches 3. 15 v . there is a 20 0mv hysteresis on this input, which requ ires the input to fall below 2.95 v before the device will disable. v bat over - voltage protection the ts 5 2002 has an output protection circuit designed to shutdown the charging profile if the output voltage is greater than the termination voltage. shutting down the charging profile puts the ts 5 2002 in a fault condition.
- 8 - ts 52002 version 1. 2 specifications subject to change www.triunesystems.com copyright ? 2011 , triune systems, llc serial interface the ts5 2002 features a n i 2 c slave interface which offers advanced control and diagnostic features. i 2 c operation offers fault and warning indicators. whenever a fault is detected, the associated status bit in the status register is set and the nflt p in is pulled low. wheneve r a warning is detected, the associated status bit in the status register is set, but the nflt pin is not pulled low. reading of the status register resets the fault and warning status bits, and the nflt pin is released after all fault status bits have be en reset. i 2 c subaddress definition figure 3 : sub - address in i 2 c transmission i 2 c bus operation the ts5 2002 has a slave i 2 c interface that supports standard and fast mode data rates, auto - sequencing, and is compliant to i 2 c standard version 3.0. i 2 c is a two - wire serial interface where the two lines are serial clock (scl) and serial data (sda). sda must be connected to a positive supply through an external pull - up resistor. the devices communicating on this bus can drive the sda line low or rel ease it to high impedance. the device that initiates the i 2 c transaction becomes the master of the bus. communication is initiated by the master sending a start condition, a high - to - low transition on sda, while the scl line is high. after the start cond ition, the device address byte is sent, most significant bit (msb) first, including the data direction bit (r/nw). after receiving the valid address byte, the device responds with an acknowledge (ack). an ack is a low on sda during the high of the ack re lated clock pulse. on the i 2 c bus, during each clock pulse only one data bit is transferred. the data on the sda line must remain stable during the high pulse of the clock period, as changes in the data line at this time are interpreted as sta rt or stop control commands. a low - to - high transition on sda while the scl input is high, indicates a stop condition and is sent by the master (see figure 4 ). any number of data bytes can be transferred from the transmitter to receiver between the start and the sto p conditions. each byte of eight bits is followed by one ack bit. the sda line must be released by the transmitter before the receiver can send an ack bit. the receiver that acknowledges must pull down the sda line during the ack clock pulse, so that the sda line is stable low during the high pulse of the ack - related clock period. when a slave receiver is addressed, it must generate an ack after each byte is received. similarly, the master must generate an ack after each byte that it receives from the sl ave transmitter. to ensure proper operation, setup and hold times must be met. an end of data is signaled by the master receiver to the slave transmitter by not generating an acknowledge after the last byte has been clocked out of the slave. this is don e by the master receiver by holding the sda line high. the transmitter must then release the data line to enable the master to generate a st op condition.
- 9 - ts 52002 version 1. 2 specifications subject to change www.triunesystems.com copyright ? 2011 , triune systems, llc figure 4 : i 2 c start / stop protocol figure 5 : i 2 c data transmission timing
- 10 - ts 52002 version 1. 2 specifications subject to change www.triunesystems.com copyright ? 2011 , triune systems, llc register description (device address = 0x48) register address (hex) name description 0 00 status status bit register 1 - 31 n/a n/a registers not implemented status register (status) address C 0x00h data bit d7 d6 d5 d4 d3 d2 d1 d0 field name v ba t _ov not used not used not used tsd not used vin_uv not used read/write r r r r r r r r field name bit definition (1) v ba t_ov v bat over - voltage tsd thermal shutdown vin_uv vin under - voltage (1) faults are defined as v ba t_ov. warnings are defined as tsd , and vin_uv. faults cause the nflt pin to be pulled low, warnings do not cause the nflt pin to be pulled low. all status bits are cleared after register read access. nflt pin will go high impedance (open drain output) after the status register has been read and all status bits have been reset. configuration regist er address C 0x04h data bit d7 d6 d5 d4 d3 d2 d1 d0 field name max_chrg_curr [3:0] not used read/write r/w r/w r/w r/w r/w r/w r/w r/w field name bit definition max_chrg_curr[3:0] maximum char ge current configuration 0000 C C C C C C C C C C C C C C C C external component s election the internal compensation is optimized for a 4.7uf output capacitor and a 4.7uh inductor. to keep the output ripple low, a low esr (less than 35mohm) ceramic is recommended.
- 11 - ts 52002 version 1. 2 specifications subject to change www.triunesystems.com copyright ? 2011 , triune systems, llc package mechanical d rawings
- 12 - ts 52002 version 1. 2 specifications subject to change www.triunesystems.com copyright ? 2011 , triune systems, llc applic ation using a multi - layer pcb to maximize the efficiency of this package for application on a single layer or multi - layer pcb, certain guidelines must be followed when laying out this part on the pcb. the following are guidelines for mounting the expose d pad ic on a multi - layer pcb with ground a plane . jedec standard fr4 pcb cross - section: multi - layer board (cross - sectional view) in a multi - layer board application, the thermal vias are the primary method of heat transfer from the package thermal pad to the internal ground plane. the efficiency of this method depends on several factors, including die area, number of thermal v ias, thickness of copper, etc. package thermal pad solder pad (land pattern) thermal via's package outline package and pcb land configuration for a multi-layer pcb ( square ) package solder pad package solder pad ( bottom trace ) thermal via component traces thermal isolation power plane only 1 . 5748 mm 0 . 0 - 0 . 071 mm board base & bottom pad 0 . 5246 - 0 . 5606 mm power plane ( 1 oz cu ) 1 . 0142 - 1 . 0502 mm ground plane ( 1 oz cu ) 1 . 5038 - 1 . 5748 mm component trace ( 2 oz cu ) 2 plane 4 plane
- 13 - ts 52002 version 1. 2 specifications subject to change www.triunesystems.com copyright ? 2011 , triune systems, llc the above drawing is a representation of how the heat can be conducted aw ay from the die using an exposed pad package. each application will have different requirements and limitations and therefore the user should use sufficient copper to dissipate the power in the system. the output current rating for the linear regulators m ay have to be de - rated for ambient temperatures above 85c. the de - rate value will depend on calculated worst case power dissipation and the thermal management implementation in the application. application using a single layer pcb layout recommendatio ns for a single layer pcb: utilize as much copper area for power management. in a single layer board application the thermal pad is attached to a heat spreader (copper areas) by using low thermal impedance attachment method (solder paste or thermal conduc tive epoxy). in both of the methods mentioned above it is advisable to use as much copper traces as possible to dissipate the heat. important: if the attachment method is not implemented correctly, the functionality of the product is not guaranteed. pow er dissipation capability will be adversely affected if the device is incorrectly mounted onto the circuit board. mold compound die epoxy die attach exposed pad solder thermal vias with cu plating single layer , 2 oz cu ground layer , 1 oz cu signal layer , 1 oz cu bottom layer , 2 oz cu 20 % cu coverage 90 % cu coverage 5 % - 10 % cu coverage note : not to scale use as much copper area as possible for heat spread package thermal pad package outline
- 14 - ts 52002 version 1. 2 specifications subject to change www.triunesystems.com copyright ? 2011 , triune systems, llc legal notices information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. it is your responsibility to ensure that your application meets with your specifications. typical parameters whic h may be provided in triune systems data sheets and/or specifications can and do vary in different applica tions and actual performance may vary over time. all operating parameters, including typicals must be validated for your application by your technical experts. triune systems makes no r epresentations or warranties of any kind whether express or implied , written or oral, statutory or otherwise, related to the information, including but not limited to its condition, quality, performance, merchantability or fitness for purpose. triune systems disclaims all liability arising from this information and its us e. triune system products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to su pport or sustain life, or for any other application in which the failure o f the triune systems product could create a situation where personal injury or death may occur. should the buyer purchase or use triune systems products for any such unintended or unauthorized application, the buyer shall indemnify and hold triune systems, and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expe nses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with s uch unintended or unauthorized use, even if such claim alleges that triune systems was negligent regarding the design or manufacture of the part. no licenses are conveyed, implici tly or otherwise, under any triune systems intellectual property rights. t rademarks the triune systems? name and logo, mppt - lite?, and nanosmart? are trademarks of triune systems, llc. in the u.s.a.. all other trademarks mentioned herein are property of their respective companies. ? 2012 triune systems, llc. all rights reserv ed.

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